In a synchronous digital system, the clock signal is used to define a time reference for the movement of data within that system. The clock distribution network distributes the clock signals from transmitters to all the elements needing such signals. Substrate noise and electro magnetic interference (EMI) in high-speed transceivers is a pervasive problem, where the signals from multiple transmitters can constructively interfere with each other. Such interference limits chip performance and reduces signal to noise ratios (SNR). Typically, multiple transmit clocks are used to managed the transmit clock phase of each channel with respect to the others in order to improve chip performance and EMI, however the existence of multiple clocks consumes valuable resources such as power and chip space.
Accordingly, there is a need to develop a clocking method that limits EMI and increases SNR, while reducing power and conserving chip space.